Cache memory is a special memory used by the CPU (Central Processing Unit) of a computer for the purpose of decreasing the average time required to access memory. Cache memory is a relatively smaller and also a faster memory, which stores most frequently accessed data of the main memory. When there is request for a memory read, cache memory is checked to see whether that data exists in cache memory. If that data is in the cache memory, then there is no need to access the main memory (which takes longer time to be accessed), therefore making the average memory access time smaller. Typically, there are separate caches for data and instructions. Data cache is typically set up in a hierarchy of cache levels (sometimes called multilevel caches). L1 (Level 1) and L2 (Level 2) are the top most caches in this hierarchy of caches. L1 is the closest cache to the main memory and is the cache that is checked first. L2 cache is the next in line and is the second closest to main memory. L1 and L2 vary in access speeds, location, size and cost.
L1 Cache
L1 cache (also known as primary cache or Level 1 cache) is the top most cache in the hierarchy of cache levels of a CPU. It is the fastest cache in the hierarchy. It has a smaller size and a smaller delay (zero wait-state) because it is usually built in to the chip. SRAM (Static Random Access Memory) is used for the implementation of L1.
L2 Cache
L2 cache (also known as secondary cache or Level 2 cache) is the cache that is next to L1 in the cache hierarchy. L2 is usually accessed only if the data looking for is not found in L1. L2 is usually used to bridge the gap between the performance of the processor and the memory. L2 is typically implemented using a DRAM (Dynamic Random Access Memory). Most times, L2 is soldered on to the motherboard very close to the chip (but not on the chip itself), but some processors like Pentium Pro deviated from this standard.
What is the difference between L1 and L2 Cache?
Although both L1 and L2 are cache memories they have their key differences. L1 and L2 are the first and second cache in the hierarchy of cache levels. L1 has a smaller memory capacity than L2. Also, L1 can be accessed faster than L2. L2 is accessed only if the requested data in not found in L1. L1 is usually in-built to the chip, while L2 is soldered on the motherboard very close to the chip. Therefore, L1 has a very little delay compared to L2. Because L1 is implemented using SRAM and L2 is implemented using DRAM, L1 does not need refreshing, while L2 needs to be refreshed. If the caches are strictly inclusive, all data in L1 can be found in L2 as well. However, if the caches are exclusive, same data will not be available in both L1 and L2.